An improved Test Control Architecture and Test Control Expansion for Core-Based System Chips
نویسنده
چکیده
This paper presents improvement of a core-based chip’s test control architecture that uses Std IEEE 1149.1 TAP to access core level register Test Control Blocks (TCB). We show enhancements for the register TCB, to improve its test coverage, to enable IEEE 1149.1 compliant RUNBIST and to optimize chip level TCB access. In addition, Test Control Expansion (TCE) is presented. TCE automatically validates test control architecture in a design netlist, and is capable of calculating chip level test mode initialization sequences.
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